The present invention relates to an apparatus, a method and a program thereof capable processing a memory fault efficiently.
In an information processing apparatus such as a high-end server, it is required that system down is not caused even if a fault occurs in a memory mounted on the information processing apparatus. Therefore, a memory fault processing system is known recently which prevents system down of an information processing apparatus even if a fault occurs in a memory mounted on the information processing apparatus.
As a related technology, a memory fault processing system is known which has a memory and a spare memory, and which stores a fault memory address at which a fault has occurred, and which switches the memory to the spare memory when an accessed address corresponds to the fault memory address. As a result, it is possible to prevent system down (for example, see Japanese Patent Laid-Open No. 3-147162 (hereinafter, called as Patent Literature 1)).
As another related technology, a memory fault processing system is known which blocks a fault page when detecting a fault of a memory. This memory fault processing system holds a copy of an update image of the memory in advance, and which outputs a copy of data of a blocked fault page to a secondary storage device as a virtual memory. As a result, it is possible to prevent system down (for example, see Japanese Patent Laid-Open No. 9-81464 (hereinafter, called as Patent Literature 2).
However, the memory fault processing system described in Patent Literature 1 has a problem that, when the number of memory fault is over the number of spare memory, it is impossible to prevent system down.
In a combination of Patent Literature 1 and Patent Literature 2, a switching to spare memory and a page blocking is combined. However, there is a problem of inefficiency that a memory page corresponding to a memory where a fault has occurred is blocked though the memory where the fault occurred has been already switched to a sound spare memory.
That is, the combination of Patent Literature 1 and Patent Literature 2 can not prevent system down by efficiently combining switching to spare memory and page blocking.
An object of a certain example of the present invention is to provide an apparatus, a method and a program thereof capable of preventing a system down by efficiently combining switching to a spare memory and blocking a faulty memory page.